The present invention relates systems and methods for testing semiconductor devices in wireless communication devices.
The production of high value devices such as wireless communication integrated circuits (ICs) used in cellular telephones and walkie-talkies requires many sophisticated processes. The actual number of processing steps required varies upon the type and complexity of the circuit being built. One design trend is to place as many systems as practicable on a single IC called a system on integrated circuit (SOIC). Components fabricated on these SOIC devices typically include processors, memory devices such as random access memory (RAM) devices and non-volatile memory devices such as FLASH memory, and analog devices such as transceivers, among others.
After fabrication, the dies of each wafer are separated into individual chips for mounting and connection in a package. The mounting and connecting (bonding) steps are expensive and can approach or exceed the cost of fabrication. To avoid wasteful packaging, a test to identify nonfunctioning chips is performed during an operation known as wafer sort (also known as die sort or electrical test). Once tested, the ICs are mounted in a package and connected to the “outside” world via package connections.
The testing of each component in the IC can be complex, expensive and time-consuming. For example, for random access memory devices, a predetermined test pattern sequence is used to test each cell in the memory. The pattern may include any number of steps, each step consisting of a number of read/write sequences. A typical test method initially writes a first value to a memory cell to be tested. The test then reads that memory cell to verify that the value is stored in the memory cell. The test then writes a second value to the memory cell, where the second value is the complement of the first value. Storage of the second value is then verified. If the memory cell fails any step within the test method, the memory device is considered defective.
For flash memory testing, in order to write data into the memory, the write operation may have to be repeated multiple times on the same address. The manufacturer of the flash memory device typically specifies a maximum number of times that the operation may be repeated in order to imprint the data in the memory. If the number of repeated operations reaches this maximum without succeeding in writing the data during testing, then the device is deemed defective.
As discussed in U.S. Pat. No. 5,682,472 to Brehm, et al., a typical flash memory test system connects each flash device to its own chip select pin that enables or disables the device from recognizing any operation that is being performed on it. Each chip select pin allows several successive cycles of input to command the device to write, verify, or read. The data to be written onto the address follows the command. The entire sequence would need to be repeated for each address up to the maximum number of iterations specified. Since each device is coupled to its own chip select pin, typically only one flash memory device is operated on at one point in time per chip select pin. Additionally, because there is one signal line for each pad, and each die is connected to the tester through a complex set of probe-pins, the process of testing is necessarily serial, with one die tested at a time. Because only one chip is enabled at one point in time, the testing process can be time consuming and costly, taking more than a minute for large memory sizes.
Typically, external testers such as automatic test equipment (ATE) are used during production to test of these devices. To illustrate, at the time of filing the instant application, a typical FLASH memory for wireless application has a capacity of about sixteen megabits. Testing each cell requires approximately twenty seconds, and with special patterns and disturb tests the test can take more than one minute. In one exemplary estimate for testing cost, a typical device tester costs approximately $200,000 and depreciates in four years. Assuming 50% uptime and utilization percentage, the cost per die is approximately $0.20. These tests have to be repeated after burn-in and after packaging, so that the final cost can be as high as $0.75/die. Since the silicon cost of the die is typically $0.50 to $5, testing cost can be a significant component of the value of the device.